Pertemuan:13 (Counter)

11/02/2013 02:27:00 PM (Basic) Digital Technique 0 Comments

In this section, the discusion is about :

• Ripple Counter
• Synchronous Binary Counters
– Design with D Flip-Flops
– Design with J-K Flip-Flops
• Serial Vs. Parallel Counters
• Up-down Binary Counter
• Binary Counter with Parallel Load
• BCD Counter, Arbitrary sequence Counters
• Counters in VHDL



Counter:
• A counter is a register that goes through a predetermined sequence of states upon the application of clock pulses.

• Counters are categorized as:
– Ripple Counters: The FF output transition serves as a source for triggering other FFs. No common clock.
– Synchronous Counter: All FFs receive the common clock pulse, and the change of state is determined from the present state.

Synchronous Binary Counters:
• The design procedure for a binary counter is the same as any other synchronous sequential circuit.
• The primary inputs of the circuit are the CLK and any control signals (EN, Load, etc).
• The primary outputs are the FF outputs (present state).
• Most efficient implementations usually use TFFs or JK-FFs. We will examine JK and D flipflop designs.


BCD Counter:
• The binary counter with parallel load can be converted into a synchronous BCD counter by connecting an external AND gate to it.
• The counter starts with an all-zero output.
• As long as the output of the AND gate is 0, each positive clock pulse transition increments the counter by one.
• When the output reaches the count of 1001, both Q0 and Q3 become 1, making the output of the AND gate equal to 1. This condition makes Load active, so on the next clock transition, the counter does not count, but is loaded from its four inputs.
• The value loaded then is 0000.



You can download full chapter from this link:
BDT13-Counter