Tampilkan postingan dengan label (Basic) Digital Technique. Tampilkan semua postingan

Pertemuan:14 (Memory PLD)

 In this section, the discusion is about :

 Programmable Logic Data

Programmable Read Only Memory atau PROM merupakan kombinasi Programmable Logic Device atau PLD. Kombinasi PLD berbentuk Integrated Circuit (IC) yang tersusun dari AND – OR dan dapat di program. Terdapat 3 tipe utama kombinasional PLD yang dibedakan dari penempatan programmable connection pada susunan AND – OR.



You can download full chapter from this link:
BDT14-Memory PLD
Read More

Pertemuan:13 (Counter)


In this section, the discusion is about :

• Ripple Counter
• Synchronous Binary Counters
– Design with D Flip-Flops
– Design with J-K Flip-Flops
• Serial Vs. Parallel Counters
• Up-down Binary Counter
• Binary Counter with Parallel Load
• BCD Counter, Arbitrary sequence Counters
• Counters in VHDL



Counter:
• A counter is a register that goes through a predetermined sequence of states upon the application of clock pulses.

• Counters are categorized as:
– Ripple Counters: The FF output transition serves as a source for triggering other FFs. No common clock.
– Synchronous Counter: All FFs receive the common clock pulse, and the change of state is determined from the present state.

Synchronous Binary Counters:
• The design procedure for a binary counter is the same as any other synchronous sequential circuit.
• The primary inputs of the circuit are the CLK and any control signals (EN, Load, etc).
• The primary outputs are the FF outputs (present state).
• Most efficient implementations usually use TFFs or JK-FFs. We will examine JK and D flipflop designs.


BCD Counter:
• The binary counter with parallel load can be converted into a synchronous BCD counter by connecting an external AND gate to it.
• The counter starts with an all-zero output.
• As long as the output of the AND gate is 0, each positive clock pulse transition increments the counter by one.
• When the output reaches the count of 1001, both Q0 and Q3 become 1, making the output of the AND gate equal to 1. This condition makes Load active, so on the next clock transition, the counter does not count, but is loaded from its four inputs.
• The value loaded then is 0000.



You can download full chapter from this link:
BDT13-Counter
Read More

Pertemuan:12 (Register)

In this section, the discusion is about :

Register
Shift Registers



Register:
• Clocked sequential circuit
– No flip-flops → reduce to combinational circuit
– No combinational circuit → remain a sequential circuit

• Register: a group of flip-flops capable of storing one bit of information – n-bit register consists of a group of n flip-flops capable of storing n bits

Parallel load
• loading: the transfer of new information into a register
• parallel loading: all the bits of the register are loaded simultaneously with a common clock pulse – Load control

Approaches to register with parallel load
• controlling the clock input signal with an enabling gate: uneven propagation delays between the master clock and the inputs of flip-flops
• controlling the D inputs: ensure that all clock pulses arrive at the same time anywhere in the system

Shift Register:
Shift register: a register capable of shifting its binary information in one or both directions

• Example Fig. 6-3: each clock pulse shifts the contents of the register one bit position to the right
– serial input: determines what goes into the leftmost flip-flop
– serial output: taken from the output of the rightmost flip-flop

• Shift control: make the shift occur only with certain pulses
– inhibiting the clock
– control through the D inputs (shown later)



You can download full chapter from this link:
BDT12-Register
Read More

Pertemuan:11 (Sequential Circuit Design)

In this section, the discusion is about :

Sequential Circuit Design

The design procedure consists of the following steps:
1. Given the problem statement, derive either the state table or state diagram.
2. Derive the state table (if not derived in 1).
3. (optional) Apply state-reduction methods to reduce (if possible) the number of states.
4. Assign binary values to each state if the state table obtained in Step 2 or 3 contains letter symbols (state assignment) to derive the encoded state table.


You can download full chapter from this link:
BDT11-Sequential Circuit Design
Read More

Pertemuan:10 (Seq Circuit; Flip Flop, Latch)

In this section, the discusion is about :

Sequencial Circuit; 
-Flip Flop
-Latch


Sequencial Circuit:
• Combinational Logic:
– Output depends only on current input
– Able to perform useful operations (add/subtract/multiply/encode/decode/select[mux]/etc…)
– Require cascading of many structures
– Costly and inflexible

• Sequential Logic:
– Output depends not only on current input but also on past input values
– Store information between operations
– Need some type of memory (Register) to remember the past input values.

 Flip-Flop:
The flip-flops receive their inputs from the combinational circuit and also from a clock signal with edges (rising or falling) that occur at fixed intervals of time, as shown in the timing diagram.


Latch:
• Level triggered
• Latches are “transparent” (= any change on the inputs is seen at the outputs immediately).
• This causes synchronization problems! (not recommended for use in synchronous designs)
• Solution: use latches to create flip-flops that can respond (update) ONLY on SPECIFIC times (instead of ANY time).




You can download full chapter from this link:
BDT10-Flip Flop, Latch
Read More

Pertemuan:9 (Asinkron, Mux, DeMux)

In this section, the discusion is about :

-Rangkaian Asinkronus Sekuensial
-Multiplex(Mux)
-De-Multiplxer(DeMux)

Rangkaian Asinkronus Sekuensial
Rangkaian sekuensial asinkron tergantung pada signal input eksternal untuk melakukan oengubahan yang ditentukan oleh variabel state. Setiap signal yang tidak disinkronkan (dengan clock) disebut ASINKRON karena pengubahan dari kondisi 1 ke 0 dan sebaliknya tidak dapat di prediksi.

Rangkaian Asinkron dapat didefinisikan sebagai rangkaian dimana signal eksistensinya pada suatu saat, ditentukan oleh perubahan logika salah satu dari signal signal input eksternal. Setiap input eksternal hanya dapat berubah 1 pada 1 saat, dan rangkaian berada pada kondisi stabil (semua signal rangkaian harus berada pada kondisi stabil, yaitu mereka berada pada kondisi steady state bila ada terjadi perubahan.

 Multiplexer
• “Selects” binary information from one of many input lines and directs it to a single output line.
• Also known as the “selector” circuit,
• Selection is controlled by a particular set of inputs lines whose # depends on the # of the data input lines.
• For a 2n-to-1 multiplexer, there are 2n data input lines and n selection lines whose bit combination determines which input is selected.

De-Multiplexer
• Performs the inverse of a multiplexing operation:
– Receives data from a single line
– Transmit it to one of the 2n possible output lines
– Selection of a specific output is controlled by the n select lines
– Demultiplexers are basically decoders! For example, a 2-to-4 DMUX


You can download full chapter from this link:
BDT09-Asinkron, Mux, DeMux
Read More

Pertemuan:8 (Decoder - Encoder)

In this section, the discusion is about :

• Design Procedure
• Code Converters
• Binary Decoders
– Expansion
– Circuit implementation
• Binary Encoders
• Priority Encoders

Design Procedure:
• Design of a combinational circuit is the development of a circuit from a description of its function.
• Starts with a problem specification and produces a logic diagram or set of boolean equations that represent the circuit.

Decoder:
• A combinational circuit that converts binary information from n coded inputs to a maximum 2n decoded outputs n-to- 2n decoder
• n-to-m decoder, m ≤ 2n
• Examples: BCD-to-7-segment decoder,
where n=4 and m=7

Encoder:
• An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n input lines and n output lines.
• The output lines generate the binary equivalent of the input line whose value is 1.


You can download full chapter from this link:
BDT08-Decoder and Encoder
Read More

Pertemuan:7 (Subtractor : Combinational Logic Design)

In this section, the discusion is about :

• Binary Subtraction
– 2’’s complement
– Extension to r’s complement
– Subtraction with complements
• Binary Adders/Subtractors
– Signed numbers
– Signed Addition/Subtraction
– Overflow problem
• Binary Multipliers


Binary Subtraction
Unsigned numbers: minus sign is not explicitly represented.

• Given 2 binary numbers M and N, find M-N:
– Case I: M ≥ N, thus, MSB of Borrow is 0
B 0 0 0 1 1 0
M 1 1 1 1 0 30
N -1 0 0 1 1 -19 Result is Correct
Dif 0 1 0 1 1 11
– Case II: N > M, thus MSB of Borrow is 1
B 1 1 1 0 0 0
M 1 0 0 1 1 19
N -1 1 1 1 0 -30 Result requires correction!
Dif 1 0 1 0 1 21

• In general, if N > M, Dif = M-N+2n, where n = # bits.
• In Case II of the previous example, Dif= 19-30+25 = 21.
• To correct the magnitude of Dif, which should be N-M, calculate 2n-(M-N+2n).
• This is known as the 2’’s complement of Dif.

Procedur Subtraction:
To subtract two n-bit numbers, M-N, in base 2:
– Find M-N.
– If MSB of Borrow is 0, then M ≥ N. Result is positive and correct.
– If MSB of Borrow is 1, then N > M. Result is negative and its magnitude must be corrected by subtracting it from 2n (find its 2’s complement).



You can download full chapter from this link:
BDT07-Subtractor
Read More

Pertemuan:6 (Adder : Combinational Logic Design)

In this section, the discusion is about :

Binary Addition
– Half Adder
– Full Adder
– Ripple Carry Adder
– Carry Lookahead Adder
Decimal Addition (Section 3.12)
– BCD Adder

1-bit Adder:
• Performs the addition of two binary bits.
• Four possible operations:
– 0+0=0
– 0+1=1
– 1+0=1
– 1+1=10
• Circuit implementation requires 2 outputs; one to indicate the sum and another to indicate the carry.

Half-bit Adder:
Performs 1-bit addition.
• Inputs: A0, B0
• Outputs: S0, C1

Index indicates significance,
A0 B0 S0 C1
0 0 0 0
0 1 1 0

Truth Table 0 is for LSB and 1 is for the next higher significant bit.
Boolean equations:
– S0 = A0B0’+A0’B0 = A0 Å B0
– C1 = A0B0

Full Adder
 -Full adder (for higher-order bit addition)
 -Combinational circuit that performs the additions of 3 bits (two bits and a carry-in bit)


You can download full chapter from this link
BDT06-Combinational Logic Design
Read More

Pertemuan:5 (Synchronous Sequential Logic)

In this section, the discusion is about :

Sequential Circuits
Latches
Flip-Flops
Analysis of Clocked Sequential Circuits
HDL for Sequential Circuits
State Reduction and Assignment
Design Procedure



Sequential Circuit:
Combinational circuits
-The outputs are entirely dependent on the current inputs
-Contains no storage elements, no feedback

Sequential circuits
-Consists of a combinational circuit to which storage elements are connected to form a feedback path
-Outputs are a function of both the current inputs and the present state of the storage elements

Storage/memory elements
-Capable of storing binary information
-Defining the state of the sequential circuit
-Next state is a function of external inputs and

Two major types: depending on timing of their signals
Asynchronous sequential circuits (see Chapter 9)
- The transition happens at any instant of time
- Do not use clock pulses. Change of internal state occurs-when there is a change in input variables
- Instability problem: may become unstable at times
- Storage elements work as time-delay device
- May be regarded as a combinational circuit with feedback

Synchronous sequential circuits
- The transition happens at discrete instants of time
- The circuit responds only to pulses on particular inputs
- Storage elements are affected only with the arrival of each pulse

State Reduction & Asignment
Sequential circuit analysis:
- starts from a circuit diagram and
- culminates in a state table or state diagram

Sequential circuit design:
- starts from a set of specifications and
- culminates in a logic diagram

State reduction problem: reduction of the number of flip-flops in a sequential circuit, while keeping the external input-output requirements unchanged
- m flip-flops produce 2m states
- State reduction ⇒ fewer flip-flops
- but may require more combinational gates



You can download full chapter from this link:
BDT05-Synchronous Sequential Logic
Read More

Pertemuan:4 (Gate Minimization)

In this section, the discusion is about :

The Map Method; Two-variable map and Three-variable map
Four-Variable Map
Five-variable Map
Product of Sums Simplification
Don’t-care Conditions
NAND and NOR Implementation
Other Two-Level Implementations
Exclusive-OR Function
Hardware Description Language (HDL)



The Map Method
Simplification of Boolean Expression
– Minimum # of terms, minimum # of literals
– To reduce complexity of digital logic gates
– The simplest expression is not unique

Methods:
– Algebraic minimization ⇒ lack of specific rules

Section 2.4
– Karnaugh map or K-map

Combination of 2, 4, … adjacent squares
Logic circuit ⇔ Boolean function ⇔ Truth table ⇔ K-map

Canonical form (sum of minterms, product of maxterms)
⇔ (Simplified) standard form (sum of products, product of sums)

Simplication Using Prime Implicant
Prime implicant: a product term obtained by combining the maximum possible number of adjacent squares in the map:
– A single 1 on a map represents a prime implicant if it is not adjacent to any other 1’s.
– Two adjacent 1’s form a prime implicant, provided that they are not within a group of four adjacent squares.
– Four adjacent 1’s form a prime implicant, provided that they are not within a group of eight adjacent squares.
– and so on
If a minterm in a square is covered by only one prime implicant, that prime implicant is said to be essential.


You can download full chapter from this link
BDT04-Gate Minimization
Read More

Pertemuan:3 (Combinational Logic Circuits)


In this section, the discusion is about :

Binary logic and Gates
Boolean Algebra; Basic Properties, Algebraic Manipulation
Standard and Canonical Forms; Minterms and Maxterms (Canonical forms), SOP and POS (Standard forms)
KarnaughMaps (K-Maps); 2, 3, 4, and 5 variable maps, Simplification using K-Maps
K-Map Manipulation; Implicants: Prime, Essential, Don’t Cares



Deals with binary variables that take 2 discrete values (0 and 1), and with logic operations. Three basic logic operations: AND, OR, NOT. Binary/logic variables are typically. represented as letters: A,B,C,…,X,Y,Z

1-bit logic AND resembles binary
multiplication:
0 • 0 = 0, 0 • 1 = 0,
1 • 0 = 0, 1 • 1 = 1

1-bit logic OR resembles binary
addition, except for one operation:
0 + 0 = 0, 0 + 1 = 1,
1 + 0 = 1, 1 + 1 = 1 (≠ 102)



You can download full chapter from this link: BDT03-Combinational Logic Circuits
Read More

Pertemuan:2 (Boolean Algebra and Logic Gates)

In this section, the discusion is about :

 • Basic Definitions
• Axiomatic Definition of Boolean Algebra
• Basic Theorems and Properties
• Boolean Functions
• Canonical and Standard Forms
• Other Logic Operations
• Digital Logic Gates
• Integrated Circuits



• Boolean Algebra (formulated by E.V. Huntington, 1904)
A set of elements B={0,1} and two binary operators + and ‧

• Huntington postulates
1. Closure w.r.t. the operator + (‧)
x, y ∈ B ⇒ x+y ∈B; x, y ∈ B ⇒ x‧y ∈B

2. Associative w.r.t. + (‧)
(x+y)+z = x + (y + z); (x‧y)‧z = x ‧ (y‧z)

3. Commutative w.r.t. + (‧)
x+y = y+x; x‧y = y‧x

4. An identity element w.r.t. + (‧)
0+x = x+0 = x; 1‧x = x‧1= x

5. ∀ x ∈ B, ∃ x' ∈ B (complement of x)
x+x'=1; x‧x'=0

6. ‧ is distributive over + : x‧(y+z)=(x‧y)+(x‧z)
+ is distributive over ‧: x+ (y‧z)=(x+ y)‧(x+ z)

Duality principle: remains

Operator Precedence; parenthese, NOT, AND, OR



You can download full chapter from this link: BDT02-Boolean Algebra and Logic Gates
Read More

Pertemuan 1 : Logics (Digital Logic, Binary System)




Dari bahasa Yunani logos Ilmu untuk berfikir dan menalar dengan benar (sehingga didapatkan kesimpulan yang absah). Manusia mampu mengembangkan pengetahuan karena mempunyai bahasa dan kemampuan menalar.Untuk dapat menarik konklusi yang tepat, diperlukan kemampuan menalar. Kemampuan menalar adalah kemampuan untuk menarik konklusi yang tepat dari bukti-bukti yang ada, dan menurut aturan-aturan tertentu. Logika bisa merupakan cabang filosofi dan bisa juga cabang dari matematika. Logika terkategori matematika murni karena matematika adalah logika yang tersistematisasi.



Logika alamiah adalah kinerja akal budi manusia yang berpikir secara tepat dan lurus sebelum dipengaruhi oleh keinginan-keinginan dan kecenderungankecenderungan yang subyektif. Kemampuan logika alamiah manusia ada sejak lahir.

Logika ilmiah merupakan tahap memperhalus, mempertajam pikiran serta akal budi. Logika ilmiah menjadi ilmu khusus yang merumuskan azas-azas yang harus ditepati dalam setiap pemikiran. Berkat pertolongan logika ilmiah inilah akal budi dapat bekerja dengan lebih tepat, lebih teliti, lebih mudah dan lebih aman. Logika ilmiah dimaksudkan untuk menghindarkan kesesatan atau, paling tidak, dikurangi.

Logika proposisional– Fokus utama logika ini pada pernyataan-pernyataan yang dapat digolongkan dalam pengertian proposisiproposisi.



Logika predikat– Penyataan-pernyataan yang tidak dapat digolongkan sebagai proposisi, dan tidak dapat diproses dengan logika proposisional, akan ditangani logika predikat yang memfokuskan diri pada predikat yang selalu menyertai suatu pernyataan dalam bentuk kalimat.

Referensi
• Nolt, John, 1990, Schaum's Outline Of Theory And Problems of Logic 2nd Edition. McGraw-Hill.
• Nolt, John, 1990, Schaum's Outline Of Set Theory And Related Topics 2nd Edition. McGraw-Hill.
• Lipson, 1997, Schaum's Outline Of Theory And Problems of Discrete Mathematics 2nd Edition. McGraw- Hill.
• Mordechai Ben-Ari, 1948, Mathematical Logic for Computer Science, Springer.
• Srivastava,

You can download full chapter from this link
Read More
Langganan: Postingan (Atom)